A team of researchers based out of Brigham Young University in Utah have developed an ADC (analogue-to-digital converter) microchip which they claim is the most efficient of its kind.
A team at Brigham Young University claims to have developed the world's most efficient microchip. Credit: Brigham Young University
ADC microchips are commonly found in modern electronics devices with companies such as Apple and Samsung constantly competing to develop increasingly efficient chips for use in their products.
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The researchers claim power-efficient chips such as the one they have developed may help end the semiconductor shortage. Chips such as these constantly have their design modified in order to maximise battery life.
The new BYU chip consumes only 21 milliwatts of power at 10 GHz for ultra wide-band wireless communication. The project's lead Professor Wood Chiang, PhD claims many current ADC models will consume multiple times this, with a potential to consume Watts of power at comparable speeds.
Chiang, a professor for BYU's Department of Electrical and Computer Engineering said: "Many research groups worldwide focus on ADCs; it's like a competition of who can build the world's fastest and most fuel-efficient car.
"It is very difficult to beat everyone else around the world, but we managed to do just that."
The professor co-developed the design for the chip alongside BYU student Eric Swindlehurst and a team of students.
Professor Wood Chiang PhD led the project to develop the ADC chip. Credit: Brigham Young University
A central challenge constantly facing researchers is the increasing bandwidth speeds within communications systems leading to circuits consuming more power.
Chiang, Swindlehurst, and their team set out to solve the problem by focusing on a key part of the ADC circuit called the DAC, which is a central piece that stands for the exact reverse of ADC - a digital-to-analogue converter.
They also grouped unit capacitors differently from the conventional method, placing together unit capacitors that are part of the same bit in the DAC rather than having them interleaved throughout.
This enabled them to significantly reduced power consumption while increasing speed owing to the lower parasitic capacitance of the bottom plate.
Finally, they also used a dual-pathed bootstrapped switch, with each path being able to be optimised separately. This method increases the speed but doesn't require additional hardware because it involves splitting existing devices and making route changes in the circuit.
"We've proven the technology of the chip here at BYU and there is no question about the efficacy of this particular technique," Chiang added. "This work really pushes the envelope of what's possible and will result in a lot of conveniences for consumers.
"Your Wi-Fi will continue to get better because of this technology, you'll have faster upload and download speeds and you can watch 4K or even 8K with little to no lag while maintaining battery life."
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Chiang hinted the increased bandwidth allowance could see these ADC chips used in self-driving cars or wireless "smart" tech such as glasses or contact lenses.
The more sophisticated design can allow for thousands of connections at once, he claimed. Any mistakes could have taken at least a year to correct.
- The team's work was published in the IEEE Journal of Solid-State Circuits.
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